To keep pace with the capability of electronic systems, such as personal computers and electronic communication devices, volatile semiconductor memory devices (such as static random access memories (SRAMs)) can be made faster and more highly integrated. Accordingly, the layout of memory cells and functional circuits connected to the memory cells can be arranged according to a scaled-down critical dimension. It is known that the layout of circuit lines in a functional circuit region of an SRAM may be a factor in the integration thereof. The functional circuit region is sometimes referred to as a peripheral circuit region, namely, a cell core region, which is adjacent to a cell region including scaled-down memory cells. The functional circuit region can include a column path circuit (also referred to as a column select circuit, which can operate as part of a column address decoder) functioning as an interface circuit that drives a unit memory cell.
In the case where a design rule is less than 80 nanometers, normally, six transistors of a full CMOS SRAM cell may be laid out on different layers (i.e., in three dimensions) rather than on the same layer. As a result, if the cell pitch of the SRAM cell is further scaled down to a resolution limitation of a photolithography process, it may be difficult to layout the P- and N-type metal oxide semiconductor (MOS) transistors (such as P1 to P4 and N1 to N4) constituting the column path circuit, and the lines 10 and 11, PBL0 to PBL3, and GBL connected thereto as shown in FIG. 1.
Thus, as semiconductor memory devices become faster and more highly integrated, there may be a need for more efficient layout of circuits. In particular, with the advent of a so-called three-dimensional memory cells in which transistors constituting the SRAM memory cell are laid out on different layers, the cell core region which is connected to the memory cell, may need to be implemented in a smaller area without the degradation of functionality of the memory cell circuit.